| 1 | // RUN: %clang_cc1 -triple arm64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s |
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| 2 | |
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| 3 | // The only part clang really deals with is the lvalue/rvalue |
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| 4 | // distinction on constraints. It's sufficient to emit llvm and make |
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| 5 | // sure that's sane. |
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| 6 | |
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| 7 | long var; |
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| 8 | |
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| 9 | void test_generic_constraints(int var32, long var64) { |
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| 10 | asm("add %0, %1, %1" : "=r"(var32) : "0"(var32)); |
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| 11 | // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32* |
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| 12 | // CHECK: call i32 asm "add $0, $1, $1", "=r,0"(i32 [[R32_ARG]]) |
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| 13 | |
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| 14 | asm("add %0, %1, %1" : "=r"(var64) : "0"(var64)); |
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| 15 | // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i64, i64* |
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| 16 | // CHECK: call i64 asm "add $0, $1, $1", "=r,0"(i64 [[R32_ARG]]) |
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| 17 | |
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| 18 | asm("ldr %0, %1" : "=r"(var32) : "m"(var)); |
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| 19 | asm("ldr %0, [%1]" : "=r"(var64) : "r"(&var)); |
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| 20 | // CHECK: call i32 asm "ldr $0, $1", "=r,*m"(i64* @var) |
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| 21 | // CHECK: call i64 asm "ldr $0, [$1]", "=r,r"(i64* @var) |
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| 22 | } |
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| 23 | |
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| 24 | float f; |
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| 25 | double d; |
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| 26 | void test_constraint_w() { |
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| 27 | asm("fadd %s0, %s1, %s1" : "=w"(f) : "w"(f)); |
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| 28 | // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f |
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| 29 | // CHECK: call float asm "fadd ${0:s}, ${1:s}, ${1:s}", "=w,w"(float [[FLT_ARG]]) |
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| 30 | |
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| 31 | asm("fadd %d0, %d1, %d1" : "=w"(d) : "w"(d)); |
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| 32 | // CHECK: [[DBL_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d |
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| 33 | // CHECK: call double asm "fadd ${0:d}, ${1:d}, ${1:d}", "=w,w"(double [[DBL_ARG]]) |
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| 34 | } |
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| 35 | |
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| 36 | void test_constraints_immed(void) { |
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| 37 | asm("add x0, x0, %0" : : "I"(4095) : "x0"); |
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| 38 | asm("and w0, w0, %0" : : "K"(0xaaaaaaaa) : "w0"); |
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| 39 | asm("and x0, x0, %0" : : "L"(0xaaaaaaaaaaaaaaaa) : "x0"); |
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| 40 | // CHECK: call void asm sideeffect "add x0, x0, $0", "I,~{x0}"(i32 4095) |
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| 41 | // CHECK: call void asm sideeffect "and w0, w0, $0", "K,~{w0}"(i32 -1431655766) |
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| 42 | // CHECK: call void asm sideeffect "and x0, x0, $0", "L,~{x0}"(i64 -6148914691236517206) |
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| 43 | } |
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| 44 | |
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| 45 | void test_constraint_S(void) { |
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| 46 | int *addr; |
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| 47 | asm("adrp %0, %1\n\t" |
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| 48 | "add %0, %0, :lo12:%1" : "=r"(addr) : "S"(&var)); |
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| 49 | // CHECK: call i32* asm "adrp $0, $1\0A\09add $0, $0, :lo12:$1", "=r,S"(i64* @var) |
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| 50 | } |
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| 51 | |
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| 52 | void test_constraint_Q(void) { |
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| 53 | int val; |
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| 54 | asm("ldxr %0, %1" : "=r"(val) : "Q"(var)); |
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| 55 | // CHECK: call i32 asm "ldxr $0, $1", "=r,*Q"(i64* @var) |
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| 56 | } |
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| 57 | |
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| 58 | void test_gcc_registers(void) { |
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| 59 | register unsigned long reg0 asm("r0") = 0; |
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| 60 | register unsigned long reg1 asm("r1") = 1; |
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| 61 | register unsigned int reg29 asm("r29") = 2; |
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| 62 | register unsigned int reg30 asm("r30") = 3; |
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| 63 | |
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| 64 | // Test remapping register names in register ... asm("rN") statments. |
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| 65 | // rN register operands in these two inline assembly lines |
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| 66 | // should get renamed to valid AArch64 registers. |
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| 67 | asm volatile("hvc #0" : : "r" (reg0), "r" (reg1)); |
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| 68 | // CHECK: call void asm sideeffect "hvc #0", "{x0},{x1}" |
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| 69 | asm volatile("hvc #0" : : "r" (reg29), "r" (reg30)); |
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| 70 | // CHECK: call void asm sideeffect "hvc #0", "{fp},{lr}" |
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| 71 | |
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| 72 | // rN registers when used without register ... asm("rN") syntax |
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| 73 | // should not be remapped. |
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| 74 | asm volatile("mov r0, r1\n"); |
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| 75 | // CHECK: call void asm sideeffect "mov r0, r1\0A", ""() |
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| 76 | } |
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| 77 | |
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