| 1 | // REQUIRES: arm-registered-target |
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| 2 | // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ |
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| 3 | // RUN: -target-abi apcs-gnu \ |
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| 4 | // RUN: -target-cpu cortex-a8 \ |
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| 5 | // RUN: -mfloat-abi soft \ |
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| 6 | // RUN: -target-feature +soft-float-abi \ |
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| 7 | // RUN: -ffreestanding \ |
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| 8 | // RUN: -emit-llvm -w -o - %s | FileCheck %s |
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| 9 | |
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| 10 | #include <arm_neon.h> |
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| 11 | |
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| 12 | // Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon |
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| 13 | // intrinsics with <2 x i64> vectors to avoid poor code for i64 in the backend. |
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| 14 | void t1(uint64_t *src, uint8_t *dst) { |
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| 15 | // CHECK: @t1 |
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| 16 | uint64x2_t q = vld1q_u64(src); |
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| 17 | // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8 |
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| 18 | vst1q_lane_u64(dst, q, 1); |
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| 19 | // CHECK: bitcast <16 x i8> %{{.*}} to <2 x i64> |
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| 20 | // CHECK: shufflevector <2 x i64> |
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| 21 | // CHECK: call void @llvm.arm.neon.vst1.p0i8.v1i64 |
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| 22 | } |
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| 23 | |
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| 24 | void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) { |
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| 25 | // CHECK: @t2 |
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| 26 | uint64x2_t q = vld1q_u64(src1); |
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| 27 | // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8 |
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| 28 | q = vld1q_lane_u64(src2, q, 0); |
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| 29 | // CHECK: shufflevector <2 x i64> |
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| 30 | // CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8 |
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| 31 | // CHECK: shufflevector <1 x i64> |
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| 32 | *dst = q; |
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| 33 | // CHECK: store <2 x i64> |
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| 34 | } |
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| 35 | |
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