| 1 | // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \ |
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| 2 | // RUN: | FileCheck %s |
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| 3 | |
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| 4 | // This checks that the frontend will accept inline asm constraints |
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| 5 | // c', 'l' and 'x'. |
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| 6 | |
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| 7 | int main() |
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| 8 | { |
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| 9 | // 'c': 16 bit address register for Mips16, GPR for all others |
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| 10 | // I am using 'c' to constrain both the target and one of the source |
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| 11 | // registers. We are looking for syntactical correctness. |
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| 12 | // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}} |
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| 13 | int __s, __v = 17; |
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| 14 | int __t; |
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| 15 | __asm__ __volatile__( |
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| 16 | "addi %0,%1,%2 \n\t\t" |
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| 17 | : "=c" (__t) |
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| 18 | : "c" (__s), "I" (__v)); |
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| 19 | |
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| 20 | // 'l': lo register |
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| 21 | // We are making it clear that destination register is lo with the |
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| 22 | // use of the 'l' constraint ("=l"). |
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| 23 | // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo},~{$1}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}} |
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| 24 | int i_temp = 44; |
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| 25 | int i_result; |
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| 26 | __asm__ __volatile__( |
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| 27 | "mtlo %1 \n\t\t" |
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| 28 | : "=l" (i_result) |
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| 29 | : "r" (i_temp) |
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| 30 | : "lo"); |
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| 31 | |
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| 32 | // 'x': Combined lo/hi registers |
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| 33 | // We are specifying that destination registers are the hi/lo pair with the |
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| 34 | // use of the 'x' constraint ("=x"). |
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| 35 | // CHECK: %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r,~{$1}"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}} |
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| 36 | int i_hi = 3; |
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| 37 | int i_lo = 2; |
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| 38 | long long ll_result = 0; |
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| 39 | __asm__ __volatile__( |
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| 40 | "mthi %1 \n\t\t" |
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| 41 | "mtlo %2 \n\t\t" |
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| 42 | : "=x" (ll_result) |
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| 43 | : "r" (i_hi), "r" (i_lo) |
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| 44 | : ); |
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| 45 | |
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| 46 | return 0; |
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| 47 | } |
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| 48 | |
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| 49 | // CHECK: attributes [[NUW]] = { nounwind } |
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| 50 | |
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