| 1 | // Test for linking with CUDA's libdevice as outlined in |
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| 2 | // http://llvm.org/docs/NVPTXUsage.html#linking-with-libdevice |
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| 3 | // |
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| 4 | // REQUIRES: nvptx-registered-target |
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| 5 | // |
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| 6 | // Prepare bitcode file to link with |
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| 7 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -emit-llvm-bc \ |
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| 8 | // RUN: -disable-llvm-passes -o %t.bc %S/Inputs/device-code.ll |
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| 9 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -emit-llvm-bc \ |
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| 10 | // RUN: -disable-llvm-passes -o %t-2.bc %S/Inputs/device-code-2.ll |
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| 11 | // |
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| 12 | // Make sure function in device-code gets linked in and internalized. |
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| 13 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \ |
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| 14 | // RUN: -mlink-builtin-bitcode %t.bc -emit-llvm \ |
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| 15 | // RUN: -disable-llvm-passes -o - %s \ |
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| 16 | // RUN: | FileCheck %s -check-prefix CHECK-IR |
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| 17 | |
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| 18 | // Make sure legacy flag name works |
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| 19 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \ |
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| 20 | // RUN: -mlink-cuda-bitcode %t.bc -emit-llvm \ |
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| 21 | // RUN: -disable-llvm-passes -o - %s \ |
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| 22 | // RUN: | FileCheck %s -check-prefix CHECK-IR |
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| 23 | // |
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| 24 | // Make sure we can link two bitcode files. |
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| 25 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \ |
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| 26 | // RUN: -mlink-builtin-bitcode %t.bc -mlink-builtin-bitcode %t-2.bc \ |
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| 27 | // RUN: -emit-llvm -disable-llvm-passes -o - %s \ |
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| 28 | // RUN: | FileCheck %s -check-prefix CHECK-IR -check-prefix CHECK-IR-2 |
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| 29 | // |
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| 30 | // Make sure function in device-code gets linked but is not internalized |
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| 31 | // without -fcuda-uses-libdevice |
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| 32 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \ |
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| 33 | // RUN: -mlink-bitcode-file %t.bc -emit-llvm \ |
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| 34 | // RUN: -disable-llvm-passes -o - %s \ |
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| 35 | // RUN: | FileCheck %s -check-prefix CHECK-IR-NLD |
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| 36 | // |
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| 37 | // Make sure NVVMReflect pass is enabled in NVPTX back-end. |
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| 38 | // RUN: %clang_cc1 -triple nvptx-unknown-cuda -fcuda-is-device \ |
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| 39 | // RUN: -mlink-builtin-bitcode %t.bc -S -o /dev/null %s \ |
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| 40 | // RUN: -mllvm -debug-pass=Structure 2>&1 \ |
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| 41 | // RUN: | FileCheck %s -check-prefix CHECK-REFLECT |
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| 42 | |
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| 43 | #include "Inputs/cuda.h" |
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| 44 | |
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| 45 | __device__ float device_mul_or_add(float a, float b); |
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| 46 | extern "C" __device__ double __nv_sin(double x); |
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| 47 | extern "C" __device__ double __nv_exp(double x); |
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| 48 | |
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| 49 | // CHECK-IR-LABEL: define void @_Z26should_not_be_internalizedPf( |
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| 50 | // CHECK-PTX-LABEL: .visible .func _Z26should_not_be_internalizedPf( |
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| 51 | __device__ void should_not_be_internalized(float *data) {} |
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| 52 | |
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| 53 | // Make sure kernel call has not been internalized. |
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| 54 | // CHECK-IR-LABEL: define void @_Z6kernelPfS_ |
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| 55 | // CHECK-PTX-LABEL: .visible .entry _Z6kernelPfS_( |
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| 56 | __global__ __attribute__((used)) void kernel(float *out, float *in) { |
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| 57 | *out = device_mul_or_add(in[0], in[1]); |
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| 58 | *out += __nv_exp(__nv_sin(*out)); |
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| 59 | should_not_be_internalized(out); |
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| 60 | } |
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| 61 | |
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| 62 | // Make sure device_mul_or_add() is present in IR, is internal and |
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| 63 | // calls __nvvm_reflect(). |
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| 64 | // CHECK-IR-LABEL: define internal float @_Z17device_mul_or_addff( |
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| 65 | // CHECK-IR-NLD-LABEL: define float @_Z17device_mul_or_addff( |
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| 66 | // CHECK-IR: call i32 @__nvvm_reflect |
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| 67 | // CHECK-IR: ret float |
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| 68 | |
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| 69 | // Make sure we've linked in and internalized only needed functions |
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| 70 | // from the second bitcode file. |
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| 71 | // CHECK-IR-2-LABEL: define internal double @__nv_sin |
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| 72 | // CHECK-IR-2-LABEL: define internal double @__nv_exp |
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| 73 | // CHECK-IR-2-NOT: double @__unused |
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| 74 | |
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| 75 | // Verify that NVVMReflect pass is among the passes run by NVPTX back-end. |
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| 76 | // CHECK-REFLECT: Replace occurrences of __nvvm_reflect() calls with 0/1 |
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| 77 | |
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