| 1 | // RUN: %clang_cc1 -ffreestanding -fsyntax-only -verify -triple arm %s |
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| 2 | |
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| 3 | void string_literal(unsigned v) { |
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| 4 | __builtin_arm_wsr(0, v); // expected-error {{expression is not a string literal}} |
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| 5 | } |
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| 6 | |
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| 7 | void wsr_1(unsigned v) { |
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| 8 | __builtin_arm_wsr("sysreg", v); |
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| 9 | } |
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| 10 | |
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| 11 | void wsrp_1(void *v) { |
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| 12 | __builtin_arm_wsrp("sysreg", v); |
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| 13 | } |
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| 14 | |
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| 15 | void wsr64_1(unsigned long v) { |
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| 16 | __builtin_arm_wsr64("sysreg", v); //expected-error {{invalid special register for builtin}} |
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| 17 | } |
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| 18 | |
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| 19 | unsigned rsr_1() { |
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| 20 | return __builtin_arm_rsr("sysreg"); |
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| 21 | } |
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| 22 | |
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| 23 | void *rsrp_1() { |
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| 24 | return __builtin_arm_rsrp("sysreg"); |
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| 25 | } |
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| 26 | |
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| 27 | unsigned long rsr64_1() { |
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| 28 | return __builtin_arm_rsr64("sysreg"); //expected-error {{invalid special register for builtin}} |
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| 29 | } |
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| 30 | |
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| 31 | void wsr_2(unsigned v) { |
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| 32 | __builtin_arm_wsr("cp0:1:c2:c3:4", v); |
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| 33 | } |
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| 34 | |
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| 35 | void wsrp_2(void *v) { |
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| 36 | __builtin_arm_wsrp("cp0:1:c2:c3:4", v); |
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| 37 | } |
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| 38 | |
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| 39 | void wsr64_2(unsigned long v) { |
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| 40 | __builtin_arm_wsr64("cp0:1:c2:c3:4", v); //expected-error {{invalid special register for builtin}} |
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| 41 | } |
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| 42 | |
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| 43 | unsigned rsr_2() { |
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| 44 | return __builtin_arm_rsr("cp0:1:c15:c15:4"); |
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| 45 | } |
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| 46 | |
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| 47 | void *rsrp_2() { |
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| 48 | return __builtin_arm_rsrp("cp0:1:c2:c3:4"); |
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| 49 | } |
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| 50 | |
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| 51 | unsigned long rsr64_2() { |
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| 52 | return __builtin_arm_rsr64("cp0:1:c2:c3:4"); //expected-error {{invalid special register for builtin}} |
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| 53 | } |
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| 54 | |
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| 55 | void wsr_3(unsigned v) { |
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| 56 | __builtin_arm_wsr("cp0:1:c2", v); //expected-error {{invalid special register for builtin}} |
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| 57 | } |
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| 58 | |
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| 59 | void wsrp_3(void *v) { |
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| 60 | __builtin_arm_wsrp("cp0:1:c2", v); //expected-error {{invalid special register for builtin}} |
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| 61 | } |
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| 62 | |
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| 63 | void wsr64_3(unsigned long v) { |
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| 64 | __builtin_arm_wsr64("cp0:1:c2", v); |
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| 65 | } |
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| 66 | |
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| 67 | unsigned rsr_3() { |
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| 68 | return __builtin_arm_rsr("cp0:1:c2"); //expected-error {{invalid special register for builtin}} |
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| 69 | } |
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| 70 | |
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| 71 | void *rsrp_3() { |
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| 72 | return __builtin_arm_rsrp("cp0:1:c2"); //expected-error {{invalid special register for builtin}} |
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| 73 | } |
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| 74 | |
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| 75 | unsigned long rsr64_3() { |
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| 76 | return __builtin_arm_rsr64("cp0:1:c15"); |
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| 77 | } |
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| 78 | |
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| 79 | unsigned rsr_4() { |
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| 80 | return __builtin_arm_rsr("0:1:2:3:4"); //expected-error {{invalid special register for builtin}} |
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| 81 | } |
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| 82 | |
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| 83 | unsigned rsr_5() { |
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| 84 | return __builtin_arm_rsr("cp0:1:c2:c3:8"); //expected-error {{invalid special register for builtin}} |
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| 85 | } |
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| 86 | |
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| 87 | unsigned rsr_6() { |
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| 88 | return __builtin_arm_rsr("cp0:8:c1:c2:3"); //expected-error {{invalid special register for builtin}} |
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| 89 | } |
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| 90 | |
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| 91 | unsigned rsr_7() { |
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| 92 | return __builtin_arm_rsr("cp0:1:c16:c16:2"); //expected-error {{invalid special register for builtin}} |
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| 93 | } |
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| 94 | |
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| 95 | void *rsrp_4() { |
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| 96 | return __builtin_arm_rsrp("0:1:2:3:4"); //expected-error {{invalid special register for builtin}} |
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| 97 | } |
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| 98 | |
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| 99 | unsigned long rsr64_4() { |
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| 100 | return __builtin_arm_rsr64("0:1:2"); //expected-error {{invalid special register for builtin}} |
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| 101 | } |
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| 102 | |
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| 103 | unsigned long rsr64_5() { |
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| 104 | return __builtin_arm_rsr64("cp0:8:c1"); //expected-error {{invalid special register for builtin}} |
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| 105 | } |
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| 106 | |
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| 107 | unsigned long rsr64_6() { |
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| 108 | return __builtin_arm_rsr64("cp0:1:c16"); //expected-error {{invalid special register for builtin}} |
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| 109 | } |
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| 110 | |
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